1. Field of Technology
Embodiments generally relate to varying the propagation delay in a circuit by modulating a power supply voltage of the circuit.
2. Background
A typical system on a chip (SOC) includes various logic blocks, any of which may also include a pipeline of timing elements such as latches and flip-flops. A pipeline of timing elements is typically connected in series, where the data output of one timing element is connected to the data input of a subsequent timing element. In a pipeline of timing elements, a hold time violation occurs when the data input of a pipeline timing element switches in the current clock cycle before the end of a hold time required to reliably store the data from the previous clock cycle. Hold time violations limit the maximum operating clock frequency of the SOC. Hold time violations may cause chip failures at low frequencies as well as high frequencies. Unlike cycle time or setup time violations, hold time violations typically cannot be fixed by lowering the frequency or raising the operating voltage.
Hold time violations are generally occur when multiple data paths are used between timing elements, some data paths including fewer logic elements between the timing elements (e.g., shorter data paths) than other data paths (e.g., longer data path). Conventionally, hold time violations are resolved by inserting delay elements in the shorter data paths to increase the propagation delay of such shorter data paths to avoid premature switching of the data input before the clock signal. However, the added delay elements take up additional die area and increase power consumption of a circuit.